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Wrote

I'm after an asynchronous 9-bit ripple-style counter that I can bit-test (or equivalent) 9 times during each loop, each time to do one of two actions half the time (ie calculated with each extreme of the tolerance) for worst-case circuit analysis.

This may be better achieved via dec2bin() with a constant 9-bit length output so that the 2^n check work consistently (ie string position tests).

FYI (reference only): https://k6jca.blogspot.c...worst-case-circuit.html. The need is for X-Y style visualization that LTSpice can't provide.

Thanks for the link. I'm aware of LTspice.
From very young, my life switched from Electronics to Process Control.
In short, LTspice works around hysteresis of a circuit design.
In other words, hysteresis becomes the critical region.
Home made demo Attached.
Take care Down Under, as we view you from up here.

Stat Hysterisis TYPICAL.sm (72 KiB) downloaded 54 time(s).

Wrote

Thank you so much overlord, that is both elegant and perfect!

Glad to hear I could help.
Yet this topic is started to fill with Jean's unnecessary posts.